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features ? secondary side high speed sr controller ? dcm, crcm and ccm flyback topologies ? 200v proprietary ic technology ? max 500khz switching frequency ? anti-bounce logic and uvlo protection ? 7a peak turn off drive current ? micropower start-up & ultra low quiescent current ? 10.7/14.5v gate drive clamp smartrectifier tm control ic IR1167ASPBF ir1167bspbf www.irf.com 1 ir1167 application diagram description ir1167s is a smart secondary side driver ic designed to drive n-channel power mosfets used as synchronous rectifiers in isolated flyback converters. the ic can control one or more paralleled n-mosfets to emulate the behavior of schottky diode rectifiers. the drain to source voltage is sensed differentially to determine the polarity of the current and turn the power switch on and off in proximity of the zero current transi- tion. ruggedness and noise immunity are accomplished using an advanced blanking scheme and double-pulse suppression which allow reliable operation in continuous, discontinuous and critical current mode operation and both fixed and variable frequency modes. package 8-lead soic ? 50ns turn-off propagation delay ? vcc range from 11.3v to 20v ? direct sensing of mosfet drain voltage ? minimal component count ? simple design ? lead-free ? compatible with 1w standby, energy star, cecp, etc. rmot cdc rg vd 5 vs 6 mot 3 ovt 2 en 4 gnd 7 vgate 8 vcc 1 u1 ir1167s q1 xfm co l o a d rdc vin rtn ci rs cs data sheet pd60254f pdf created with pdffactory trial version www.pdffactory.com
ir1167as/bs www.irf.com 2 * per eia/jesd22-a114-b( discharging a 100pf capacitor through a 1.5k w series resistor). stress beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions are not implied. all voltages are absolute voltages referenced to gnd. thermal resistance and power dissipation are measured under board mounted and still air conditions. absolute maximum ratings parameters symbol min. max. units supply voltage v cc -0.3 20 v enable voltage v en -0.3 20 v cont. drain sense voltage v d -3 200 v pulse drain sense voltage v d -5 200 v source sense voltage v s -3 20 v gate voltage v gate -0.3 20 v operating junction temperature t j -40 150 c storage temperature t s -55 150 c thermal resistance r q ja 128 c/w package power dissipation p d 970 mw esd protection v esd 2 kv switching frequency fsw 500 khz soic-8, t amb =25c human body model* v cc =20v, gate off soic-8 remarks pdf created with pdffactory trial version www.pdffactory.com
irf.com 3 ir1167as/bs electrical characteristics the electrical characteristics involve the spread of values guaranteed within the specified supply voltage and junction temperature range t j from ? 25 c to 125c. typical values represent the median values, which are related to 25c. if not otherwise stated, a supply voltage of v cc =15v is assumed for test condition. supply section parameters symbol min. typ. max. units supply voltage operating range v cc 12 18 v v cc turn on threshold v cc on 9.8 10.5 11.3 v v cc turn off threshold (under voltage lock out) v cc turn on/off hysteresis v cc hyst 1.4 1.55 1.7 v 8.5 10 50 65 10.3 12 66 80 quiescent current i qcc 1.8 2.2 ma start-up current i cc start 100 200 a sleep current i sleep 150 200 a enable voltage high v enhi 2.25 2.75 3.1 v enable voltage low v enlo 1.3 1.6 1.9 v enable pull-up resistance r en 1.5 m w comparator section parameters symbol min. typ. max. units -7 -3.5 0 turn-off threshold v th1 -15 -10.5 -7 mv -23 -19 -15 turn-on threshold v th2 -150 -50 mv hysteresis v hyst 55 mv input bias current i ibias1 1 7.5 a input bias current i ibias2 30 100 a comparator input offset v offset 2 mv input cm voltage range v cm -0.15 2 v one-shot section parameters symbol min. typ. max. units blanking pulse duration t blank 10 15 20 s 2.5 v 5.4 v hysteresis v hyst3 40 mv minimum on time section parameters symbol min. typ. max. units 190 240 290 ns 2.4 3 3.6 s gbd v d = -50mv v ovt floating, v s =0v ovt = v cc, v s =0v gbd ovt = 0v, v s =0v ir1167a c load =1nf, fsw = 400khz c load =10nf, f sw = 400khz ir1167b c load =1nf, fsw = 400khz v cc uvlo i cc 8.4 9.7 9 v cc =v cc on - 0.1v remarks reset threshold v th3 operating current v cc =20v - gbd v cc =10v - gbd v d = 200v v en =0v, v cc =15v remarks gbd c load =10nf, f sw = 400khz ma minimum on time t onmin remarks r mot =75k w, v cc =12v r mot =5k w, v cc =12v v cc =10v - gbd remarks 2.15 3.2 1.2 2.15 2 2.15 3.2 9 25 pdf created with pdffactory trial version www.pdffactory.com
ir1167as/bs www.irf.com 4 state and transitions diagram power on gate inactive uvlo mode vcc < vccon gate inactive icc max = 200ua normal gate active vcc > vccon and enable high vcc < vccuvlo or enable low ** guaranteed by design minimum on time section parameters symbol min. typ. max. units 190 240 290 ns 2.4 3 3.6 s minimum on time t onmin remarks r mot =75k w, v cc =12v r mot =5k w, v cc =12v gate driver section parameters symbol min. typ. max. units gate low voltage v glo 0.3 0.5 v gate high voltage v gth 9.5 10.7 12.5 v gate high voltage v gth 12.5 14.5 16.5 v rise time t r1 18 ns t r2 125 ns fall time t f1 10 ns t f2 30 ns turn on propagation delay t don 60 80 ns turn off propagation delay t doff 40 65 ns pull up resistance r up 4 w pull down resistance r down 0.7 w output peak current (source) i o source 2 a output peak current (sink) i o sink 7 a ir1167a - v cc =12v-18v (internally clamped) remarks i gate = 200ma i gate = -200ma ir1167b - v cc =12v-18v (internally clamped) c load = 1nf, v cc =12v c load = 1nf, v cc =12v c load = 10nf, v cc =12v c load = 10nf, v cc =12v c load = 10nf - gbd c load = 10nf - gbd v ds to v gate -100mv overdrive v ds to v gate -100mv overdrive i gate = 1a - gbd 9 12 pdf created with pdffactory trial version www.pdffactory.com
www.irf.com 5 ir1167as/bs lead assignments & definitions block diagram lead assignment pin# symbol description 1 2 3 4 5 6 7 8 vcc ovt mot en vd vs gnd gate supply voltage offset voltage trimming minimum on time enable fet drain sensing fet source sensing ground gate drive output vd gnd vgate vs vcc mot en ovt 4 3 2 1 5 6 7 8 i r 1 1 6 7 s uvlo & regulator vd vcc vth1 com ena vgate vs vth3 vth1 vth2 vth3 vgate v ds mot ovt min off time reset min on time reset driver vcc vcc pdf created with pdffactory trial version www.pdffactory.com
ir1167as/bs www.irf.com 6 gnd: ground this is ground potential pin of the integrated control circuit. the internal devices and gate driver are referenced to this point. mot: minimum on time the mot programming pin controls the amount of minimum on time. once v th2 is crossed for the first time, the gate signal will become active and turn on the power fet. spurious ringings and oscillations can trigger the input comparator off. the mot blanks the input comparator keeping the fet on for a minimum time. the mot is programmed between 200ns and 3us (typ.) by using a resistor referenced to gnd. ovt: offset voltage trimming the ovt pin will program the amount of input offset voltage for the turn-off threshold v th1 . the pin can be optionally tied to ground, to vcc or left floating, to select 3 ranges of input offset trimming. this programming feature allows for accomodating different rdson mosfets. gate: gate drive output this is the gate drive output of the ic. drive voltage is internally limited and provides 2a peak source and 7a peak sink capability. although this pin can be directly connected to the power mosfet gate, the use of minimal gate resistor is recommended, expecially when putting multiple fets in parallel. care must be taken in order to keep the gate loop as short and as small as possible in order to achieve optimal switching performance. vs: source voltage sense vs is the differential sense pin for the power mosfet source. this pin must not be connected directly to the power ground pin (7) but must be used to create a kelvin contact as close as possible to the power mosfet source pin. vd: drain voltage sense vd is the voltage sense pin for the power mosfet drain. this is a high voltage pin and particular care must be taken in properly routing the connection to the power mosfet drain. additional filtering and or current limiting on this pin is not recommended as it would limit switching perfor- mance of the ic. vcc: power supply this is the supply voltage pin of the ic and it is monitored by the under voltage lockout circuit. it is possible to turn off the ic by pulling this pin below the minimum turn off threshold voltage, without damage to the ic. to prevent noise problems, a bypass ceramic capacitor connected to vcc and gnd should be placed as close as possible to the ir1167s. this pin is internally clamped. en: enable this pin is used to activate the ic ?sleep? mode by pulling the voltage level below 2.5v (typ). in sleep mode the ic will consume a minimum amount of cur- rent. however all switching functions will be disabled and the gate will be inactive. detailed pin description pdf created with pdffactory trial version www.pdffactory.com
www.irf.com 7 ir1167as/bs general description the ir1167 smart rectifier ic can emulate the operation of diode rectifier by properly driving a synchronous rectifier (sr) mosfet. the direction of the rectified current is sensed by the input comparator using the power mosfet r dson as a shunt resistance and the gate pin of the mosfet is driven accordingly. internal blanking logic is used to prevent spurious transitions and guarantee operation in continuous (ccm), discountinuous (dcm) and critical (crcm) conduction mode. states of operation uvlo/sleep mode the ic remains in the uvlo condition until the voltage on the vcc pin exceeds the vcc turn on threshold voltage, v cc on . during the time the ic remains in the uvlo state, the gate drive circuit is inactive and the ic draws a quiescent current of i cc start . the uvlo mode is accessible from any other state of operation whenever the ic supply voltage condition of vcc < v cc uvlo occurs. the sleep mode is initiated by pulling the en pin below 2.5v (typ). in this mode the ic is essentially shut down and draws a very low quiescent supply current. normal mode the ic enters in normal operating mode once the uvlo voltage has been exceeded. at this point the gate driver is operating and the ic will draw a maximum of i cc from the supply voltage source. the modes of operation for a flyback circuit differ mainly for the turn-off phase of the sr switch, while the turn-on phase of the secondary switch (which correspond to the turn off of the primary side switch) is identical. turn-on phase when the conduction phase of the sr fet is initiated, current will start flowing through its body diode, generating a negative v ds voltage across it. the body diode has generally a much higher voltage drop than the one caused by the mosfet on resistance and therefore will trigger the turn-on threshold v th2 . at that point the ir1167 will drive the gate of mosfet on which will in turn cause the conduction voltage v ds to drop down. this drop is usually accompained by some amount of ringing, that can trigger the input comparator to turn off; hence, a minimum on time (mot) blanking period is used that will maintain the power mosfet on for a minimum amount of time. the programmed mot will limit also the minimum duty v gate v th1 v th2 v th3 v ds input comparator thresholds pdf created with pdffactory trial version www.pdffactory.com
ir1167as/bs www.irf.com 8 i prim i sec v sec v prim time time t1 t2 t3 cycle of the sr mosfet and, as a consequence, the max duty cycle of the primary side switch. dcm/crcm turn-off phase once the sr mosfet has been turned on, it will remain on until the rectified current will decay to the level where v ds will cross the turn-off threshold v th1 . this will happen differently depending on the mode of operation. in dcm the current will cross the threshold with a relatively low di/dt. once the threshold is crossed, the current will start flowing again through the body diode, causing the v ds voltage to jump negative. depending on the amount of residual current, v ds may trigger once again the turn on threshold: for this reason v th2 i prim i sec v sec v prim time time t1 t2 primary and secondary currents and voltages for dcm mode primary and secondary currents and voltages for crcm mode is blanked for a certain amount of time (t blank ) after v th1 has been triggered. the blanking time is internally set. as soon as v ds crosses the positive threshold v th3 also the blanking time is terminated and the ic is ready for next conduction cycle. ccm turn-off phase in ccm mode the turn off transition is much steeper and di/dt involved is much higher. the turn on phase is identical to dcm or crcm and therefore won?t be repeated here. during the sr fet conduction phase the current will decay linearly, and so will vds on the sr fet. i prim i sec v sec v prim time time t1 t2 primary and secondary currents and voltages for ccm mode once the primary switch will start to turn back on, the sr fet current will rapidly decrease crossing v th1 and turning the gate off. the turn off speed is critical to avoid cross conduction on the primary side and reduce switching losses. also in this case a blanking period will be applied, but given the very fast nature of this transition, it will be reset as soon as v ds crosses v th3 . pdf created with pdffactory trial version www.pdffactory.com
www.irf.com 9 ir1167as/bs gate drive i sec v ds blanking time time t1 t2 v th1 v th2 v th3 10us blanking mot secondary side ccm operation secondary side dcm/crcm operation i sec v ds time time t1 t2 v th1 v th2 v th3 blanking mot time gate drive pdf created with pdffactory trial version www.pdffactory.com
ir1167as/bs www.irf.com 10 fig 2. under voltage lockout vs. temp. fig 1. supply current vs. supply voltage fig 3. v th1 vs. temp. fig 4. v th2 vs. temp. -50 0 50 100 150 temperature ( c ) 8 9 10 11 v c c u v l o t h r e s h o l d ( v ) v cc on v cc uvlo 5 10 15 20 supply voltage (v) 0.01 0.1 1 10 i s u p p l y ( m a ) -50 0 50 100 150 temperature ( c ) -30 -25 -20 -15 -10 -5 0 v t h 1 t h r e s h o l d ( m v ) ovt = gnd ovt = floating ovt = v cc -50 0 50 100 150 temperature ( c ) -150 -100 -50 0 v t h 2 t h r e s h o l d ( m v ) pdf created with pdffactory trial version www.pdffactory.com
www.irf.com 11 ir1167as/bs fig 6. v th1 vs. temp. and common mode (ovt=gnd) fig 5. comparator hysteresis vs. temp. fig 7. v th2 vs. temp. and common mode (ovt=gnd) fig 8. comparator hysteresis vs. temp. and common mode (ovt=gnd) -50 0 50 100 150 temperature ( c ) 0 50 100 c o m p a r a t o r h y s t e r e s i s v h y s t ( m v ) -50 0 50 100 150 temperature ( c ) -9 -6 -3 0 v t h 1 t h r e s h o l d ( m v ) vs = -150mv vs= 0v vs= +2v -50 0 50 100 150 temperature ( c ) -150 -100 -50 v t h 2 t h r e s h o l d ( m v ) vs = -150mv vs= 0v vs= +2v -50 0 50 100 150 temperature ( c ) -150 -100 -50 c o m p a r a t o r h y s t e r e s i s ( m v ) vs = -150mv vs= 0v vs= +2v pdf created with pdffactory trial version www.pdffactory.com
ir1167as/bs www.irf.com 12 fig 11. max. v cc voltage vs. synchronous rectifier switching freq, t j =125 c, t ic = 85 c, external r g =1 w , 1 w hexfet gate resistance included fig 9. mot vs. temp. fig 12. max. v cc voltage vs. synchronous rectifier switching freq, t j =125 c, t ic = 85 c, external r g =2 w , 1 w hexfet gate resistance included 0 50 100 150 200 drain sense voltage (v d) (v) 0 20 40 60 80 100 i n p u t b i a s c u r r e n t ( i b i a s 2 ) ( a ) t j = -25c t j = 25c t j = 125c fig 10. input bias current vs. v d . 50 100 150 200 250 300 350 400 450 500 max. synchronous hexfet switching frequency (khz) 11 12 13 14 15 16 17 18 19 20 m a x i m u m a l l o w a b l e v c c v o l t a g e ( v ) csync = 2nf csync = 5nf csync = 8nf csync = 15nf csync = 20nf 50 100 150 200 250 300 350 400 450 500 max. synchronous hexfet switching frequency (khz) 11 12 13 14 15 16 17 18 19 20 m a x i m u m a l l o w a b l e v c c v o l t a g e ( v ) csync = 2nf csync = 5nf csync = 8nf csync = 15nf csync = 20nf -50 0 50 100 150 temperature ( c ) 0 1 2 3 4 m i n i m u m o n t i m e ( s ) rmot = 5k rmot= 75k pdf created with pdffactory trial version www.pdffactory.com
www.irf.com 13 ir1167as/bs fig 13. max. v cc voltage vs. synchronous rectifier switching freq, t j =125 c, t ic = 85 c, external r g =4 w , 1 w hexfet gate resistance included fig 14. max v cc voltage vs. synchronous rectifier switching freq, t j =125 c, t ic = 85 c, external r g =6 w , 1 w hexfet gate resistance included figures 11-14 shows the maximum allowable v cc voltage vs. maximum switching frequency for different loads which are calculated using the design methodology discussed in an1087. 50 100 150 200 250 300 350 400 450 500 max. synchronous hexfet switching frequency (khz) 11 12 13 14 15 16 17 18 19 20 m a x i m u m a l l o w a b l e v c c v o l t a g e ( v ) csync = 2nf csync = 5nf csync = 8nf csync = 15nf csync = 20nf 50 100 150 200 250 300 350 400 450 500 maximum synchronous hexfet switching frequency (khz) 11 12 13 14 15 16 17 18 19 20 m a x i m u m a l l o w a b l e v c c v o l t a g e ( v ) csync = 2nf csync = 5nf csync = 8nf csync = 15nf csync = 20nf pdf created with pdffactory trial version www.pdffactory.com
ir1167as/bs www.irf.com 14 fig. 14 - v cc under voltage lockout 10% 90% t rise v th2 t fall v th1 t doff t don 50% v ds v gate fig. 15 - timing diagrams t vcc vcc on uvlo vcc uvlo normal uvlo pdf created with pdffactory trial version www.pdffactory.com
www.irf.com 15 ir1167as/bs case outline 01-6027 01-0021 11 (ms-012aa) 8-lead soic 8 7 5 6 5 d b e a e 6x h 0.25 [.010] a 6 4 3 1 2 4. outline conforms to jedec outline ms-012aa. notes: 1. dimensioning & tolerancing per asme y14.5m-1994. 2. controlling dimension: millimeter 3. dimensions are shown in millimeters [inches]. 7 k x 45 8x l 8x c y footprint 8x 0.72 [.028] 6.46 [.255] 3x 1.27 [.050] 8x 1.78 [.070] 4. outline conforms to jedec outline ms-012aa. 5 dimension does not include mold protrusions. 6 dimension does not include mold protrusions. mold protrusions not to exceed 0.25 [.010]. 7 dimension is the length of lead for soldering to a substrate. mold protrusions not to exceed 0.15 [.006]. 0.25 [.010] cab e1 a a1 8x b c 0.10 [.004] e1 d e y b a a1 h k l .189 .1497 0 .013 .050 basic .0532 .0040 .2284 .0099 .016 .1968 .1574 8 .020 .0688 .0098 .2440 .0196 .050 4.80 3.80 0.33 1.35 0.10 5.80 0.25 0.40 0 1.27 basic 5.00 4.00 0.51 1.75 0.25 6.20 0.50 1.27 min max millimeters inches min max dim 8 e c .0075 .0098 0.19 0.25 .025 basic 0.635 basic 330.00 (12.992) max. 14.40 ( .566 ) 12.40 ( .488 ) notes : 1. controlling dimension : millimeter. 2. outline conforms to eia-481 & eia-541. feed direction terminal number 1 12.3 ( .484 ) 11.7 ( .461 ) 8.1 ( .318 ) 7.9 ( .312 ) notes: 1. controlling dimension : millimeter. 2. all dimensions are shown in millimeters(inches). 3. outline conforms to eia-481 & eia-541. tape and reel information (soic 8-lead only) pdf created with pdffactory trial version www.pdffactory.com
ir1167as/bs www.irf.com 16 part marking information order information the soic-8 is msl2 qualified this product has been designed and qualified for the industrial market. data and specifications subject to change without notice. qualification standards can be found at www.irf.com world headquarters: 233 kansas street, el segundo, california 90245 tel: (310) 252-7105 data and specifications subject to change without notice. 1/2009 8-lead soic IR1167ASPBF 8-lead soic ir1167bspbf 8-lead soic tape and reel ir1167astrpbf 8-lead soic tape and reel ir1167bstrpbf ir1167a

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